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INTEGRATED CIRCUITS
74F256 Dual addressable latch
Product specification IC15 Data Handbook 1988 Nov 29
Philips Semiconductors
Philips Semiconductors
Product specification
Dual addressable latch
74F256
FEATURES
* Combines dual demultiplexer and 8-bit latch * Serial-to-parallel capability * Output from each storage bit available * Random (addressable) data entry * Easily expandable * Common reset input * Useful as dual 1-of-4 active High decoder
DESCRIPTION
The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the dual 1-of-4 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data inputs, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs.
PIN CONFIGURATION
A0 1 A1 2 Da 3 Q0a 4 Q1a 5 Q2a 6 Q3a 7 GND 8 16 V CC 15 MR 14 E 13 Db 12 Q3b 11 Q2b 10 Q1b 9 Q0b
SF00805
TYPE
TYPICAL PROPAGATION DELAY 7.0ns
TYPICAL SUPPLY CURRENT (TOTAL) 28mA
74F256
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F256N N74F256D PKG DWG #
16-pin plastic DIP 16-pin plastic SO
SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS Da, Db A0, A1 E MR Q0a - Q3a Port A, port B inputs Address inputs Enable (active Low) Master Reset inputs (active Low) Port A outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA 1.0mA/20mA
Q0b - Q3b Port B outputs NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
1988 Nov 29
2
853-0359 95207
Philips Semiconductors
Product specification
Dual addressable latch
74F256
LOGIC SYMBOL
IEC/IEEE SYMBOL
3 13 3 13 15 Z5 Z6 G4
Da 14 1 2 15 E A0 A1 MR Q0a Q1a Q2a Q3a
Db 1 0 0 G Q0b Q1b Q2b Q3b 2 1 0 3 1 2 3 14
5, 7D 1 C7 4R 4
5 6 7 6, 8D 1
4
5
6
7
9
10
11
12 0 1 2 3
C8 4R
9
10 11 12
VCC = Pin 16 GND = Pin 8
SF00806
SF00807
FUNCTION TABLE
INPUTS MR L L L L L H H H H H L X d q E H L L L L H L L L D X d d d d X d d d A0 X L H L H X L H L A1 X L L H H X L L H Q0 L Q=d L L L q0 Q=d q0 q0 OUTPUTS Q1 L L Q=d L L q1 q1 Q=d q1 Q2 L L L Q=d L q2 q2 q2 Q=d Q3 L L L L Q=d q3 q3 q3 q3 Addressable Latch Store (do nothing) OPERATING MODE Master Reset Demultiplex (active-High decoder when D=H)
H L d H H q0 q1 q2 Q=d = High voltage level = Low voltage level = Don't care = High or Low data one setup time prior to the Low-to-High Enable transition = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
1988 Nov 29
3
Philips Semiconductors
Product specification
Dual addressable latch
74F256
LOGIC DIAGRAM
12
Q3b
11
Q2b
10
Q1b
9
Q0b
7
Q3a
6
Q2a
Db
13
Da E
3 5 14 Q1a
MR A1 A0
15 2 1
4
Q0a
VCC = Pin 16 GND = Pin 8
SF00808
1988 Nov 29
4
Philips Semiconductors
Product specification
Dual addressable latch
74F256
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA
C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 4.5 2.0 0.8 -18 -1 20 70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA UNIT
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH VOL VIK II IIH IIL IOS ICC PARAMETER High-level output voltage TEST CONDITIONS1 VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX Low-level output voltage VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 Supply current (total) ICCH ICCL VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX -60 21 33 10%VCC 5%VCC 10%VCC 5%VCC MIN 2.5 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 -150 42 60 LIMITS TYP2 MAX V V V V V A A mA mA mA UNIT
mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. To reduce the effect of external noise during test. 4. Not more than one output should be shorted at a time. For testing IOS, the use of High-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1988 Nov 29
5
Philips Semiconductors
Product specification
Dual addressable latch
74F256
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPHL Propagation delay Dn to Qn Propagation delay E to Qn Propagation delay An to Qn Propagation delay MR to Qn Waveform 2 Waveform 1 Waveform 3 Waveform 4 4.0 3.0 4.5 3.0 5.0 4.5 5.0 TYP 7.0 5.0 8.0 5.0 10.0 8.5 7.0 MAX 9.5 7.0 10.5 7.0 14.0 9.5 9.0 Tamb = 0C to +70C VCC = +5V 10% CL = 50pF, RL = 500 MIN 4.0 2.5 4.5 3.0 5.0 4.0 4.5 MAX 10.0 7.5 12.0 7.5 14.5 10.0 10.0 ns ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(L) Setup time, High or Low Dn to E Hold time, High or Low Dn to E Setup time, High or Low An to E1 Hold time, High or Low An to E2 E Pulse width, Low Waveform 5 Waveform 5 Waveform 6 Waveform 6 Waveform 1 Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN 3.0 6.5 0 0 2.0 2.0 0 0 7.5 TYP MAX VCC = +5.0V 10% CL= 50pF, RL = 500 MIN 3.0 7.0 0 0 2.0 2.0 0 0 8.0 MAX ns ns ns ns ns Tamb = 0C to +70C UNIT
tw(L) MR Pulse width, Low Waveform 4 3.0 3.0 ns NOTES: 1. The Address to Enable setup time is the time before the High-to-Low Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The Address to Enable hold time is the time before the Low-to-High Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected.
1988 Nov 29
6
Philips Semiconductors
Product specification
Dual addressable latch
74F256
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
tW(L) E VM VM tPLH Qn Qn VM VM Dn VM VM
tPHL
tPHL VM
tPLH VM
SF00809
SF00810
Waveform 1. Propagation Delay, Enable Input to Output, Enable Pulse Width
Waveform 2. Propagation Delay, Data to Output
tW(L) An VM VM MR VM tPHL Qn VM VM VM VM
tPHL Qn
tPLH
SF00811
SF00812
Waveform 3. Propagation Delay Address to Output
Waveform 4. Master Reset Pulse Width and Master Reset to Output Delay
Dn VM ts(H) VM VM th(H) VM ts(L) VM th(L) VM E An VM ts VM Address Stable VM th VM
E
SF00814
Qn
Q=D
Q=D
Waveform 6. Address Setup and Hold Times
SF00813
Waveform 5. Data Setup and Hold Times
1988 Nov 29
7
Philips Semiconductors
Product specification
Dual addressable latch
74F256
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1988 Nov 29
8
Philips Semiconductors
Product specification
Dual addressable latch
74F256
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1988 Nov 29
9
Philips Semiconductors
Product specification
Dual addressable latch
74F256
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1988 Nov 29
10
Philips Semiconductors
Product specification
Dual addressable latch
74F256
NOTES
1988 Nov 29
11
Philips Semiconductors
Product specification
Dual addressable latch
74F256
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05106
Philips Semiconductors
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